TSMC is scaling 2nm (N2) production. A September 20, 2026 report from RPRNA says the ramp is pulling more demand into Taiwan materials and tools suppliers as the foundry shifts from FinFET to Gate-All-Around nanosheet transistors.
The same piece puts N2 at up to a 15% performance gain or a 30% power cut versus N3E. Those are the deltas RPRNA published. It did not list wafer starts, yield, or Apple’s A20 unit allocation for this node.
GAA adds CMP steps and chemical load
Gate-All-Around raises process complexity. RPRNA names more chemical mechanical planarization steps, tighter wafer monitoring, and heavier chemical demand as the main cost and volume drivers for the local chain.
That is a different bottleneck from the memory allocation story that has dominated phone OEM headlines this month. Logic capacity at the leading edge is its own queue, even while DRAM stays tight.
Photo: Apple
Kinik CMP share rises toward 80% on N2
Kinik supplies CMP diamond disks. RPRNA expects the company to take over 80% share at TSMC’s 2nm node, up from about 70% at 3nm. CMP content value per wafer is projected to rise 10% to 15% on N2, with more room as TSMC moves toward A16.
Phoenix Silicon International (PSI) is expanding recycled test-wafer capacity. The target in the report is 1.2 million monthly recycled wafers by late 2026. Chemical vendor New Application Materials (AEM) is shipping photoresist and rinse mixes tuned for GAA as TSMC opens two new 2nm fabs. Suntsu is also named among domestic suppliers expected to grow with the ramp.
RPRNA did not publish Kinik revenue figures, PSI’s current monthly volume, or AEM’s order book. The concrete numbers in the piece are the share step, the CMP content uplift, and the 1.2 million recycled-wafer target.
Photo: Apple
Apple already holds early TSMC capacity
Apple’s phone silicon sits on this same foundry path. Earlier this month the site covered how Samsung and Qualcomm were talking 2nm again while Apple held early TSMC capacity. Today’s supplier ramp does not restate that negotiation. It shows the materials layer catching up to N2 volume.
Premium phones still need both advanced logic and scarce DRAM. Memory pressure has already pushed smaller makers into board redesigns when allocation ran out, and CXMT’s recent LPDDR6 mass-production start did not clear Apple-related supply talk. TrendForce also lifted 2026 phone production to 1.07 billion on early component buys. None of those pieces put a Kinik share number or a PSI recycled-wafer target on TSMC’s N2 ramp.
What the report does not say
RPRNA does not give TSMC’s N2 utilization, ASP, or which smartphone SoCs are already in volume on the node. It does not name Apple, Samsung, or Qualcomm as confirmed N2 customers in that article. The public claim is the architecture shift, the performance and power ranges versus N3E, two new 2nm fabs, and the named Taiwanese tool and chemical vendors riding the ramp.
For phone brands, that still matters. If CMP disks, test wafers, and GAA chemicals stay the binding constraint at the materials layer, foundry allocation fights will sit beside the memory shortage rather than replace it.
Source: RPRNA, Sep. 20, 2026 (TSMC 2nm GAA supply-chain ramp)
