Recently, Huawei has made substantial progress in the field of chip research and development. Working hand in hand with a Chinese scientific research team, Huawei has successfully developed the world’s first two-dimensional (2D) parallel computing chip. This technology not only brings a new development direction to the semiconductor industry, but also reflects that China can still advance research and development progress in the field of 2D semiconductor research without relying on American technology.
This newly developed 2D chip is named Mengqi-1000 (English codename: Magic 1000). The research team used molybdenum disulfide, an extremely thin two-dimensional material, to build transistors. The special physical structure allows electrons to remain stable throughout the entire operation process, thus effectively overcoming the scaling challenges faced by traditional silicon materials. With this material advantage, Mengqi-1000 has successfully achieved a landmark high integration density, achieving a density of 9336 transistors per square millimeter in a small area, which is comparable to mature silicon-based chips at the same node.
In terms of specifications and architecture, Magic 1000 adopts the RISC protocol designed for efficient instruction processing, and fully integrates core modules such as instruction decoders, temporary register files, and arithmetic logic units within the chip. The chip supports parallel multi-bit data input and output and operates at a frequency of 43kHz. It is worth noting that the R&D team applied register files directly to the chipset. This design directly avoids the data delay caused by accessing the chip’s external memory, making the overall computing process smoother.
In order to ensure that this chip can maintain high stability, the engineering team introduced a multi-level collaborative optimization method and hybrid design technology to strictly control the uniformity of the transistor from the material stage. In addition, the chip abandoned the common two-row layout in the past and switched to a new three-row layout design to achieve a balance between noise tolerance and chip area.
